1/8 february 2003 n receiver and drivers meet or exceed the requirements of ansi eia/tia-644 standard: receivers low-voltage ttl (lvttl) levels designed for signaling rates up to 630mbps n operates from a single 3.3v supply n low voltage differential signaling with typical output voltage of 350mv and a 100 w load n propagation delay time: 2.2ns (typ) n electrically compatible with lvds, pecl, lvpecl, lvttl, lvcomos, gtl, btl, ctt, sstl, or hstl outputs with external network n esd protection (hbm): 7kv n bus terminal esd exceeds 7kv n so and tssop packaging description the stlvds105 is a differential line receiver and a lvttl input connected to four differential line drivers that implement the electrical characteristics of low voltage differential signaling, for point to point baseband data transmission over controlled impedance media of approximately 100 w . the transmission media can be printed-circuit board traces, backplanes, or cable. lvds, as specified in eia/tia-644 is a data signaling technique that offers low-power, low noise coupling, and switching speed to transmit data at a speed up to 630mbps at relatively long distances. the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allow extremely precise timing alignment of the signals repeated from the input. the device allows extremely precise timing alignment of the signal repeated from the input. this is particularly advantageous in distribution or expansion of signals such as clock or serial data stream. ordering codes typ e temperature range package comments STLVDS105BD -40 to 85 c so-16 (tube) 50parts per tube / 20tube per box STLVDS105BDr -40 to 85 c so-16 (tape & reel) 2500 parts per reel stlvds105btr -40 to 85 c tssop16 (tape & reel) 2500 parts per reel stlvds105 4-port lvds and 4-port ttl-to lvds repeaters sop tssop
stlvds105 2/8 pin configuration pin description functional diagram functional table l=low level, h=high level, z= high impedance absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. note 1: all voltages except differential i/o bus voltage, are with respect to the network ground terminal. pln n symbol name and function 1, 2, 3, 8 en1 to en4 enable driver inputs 6 a receiver input 7 nc not connected 9, 11, 13, 15 1z to 4z driver inputs 10, 12, 14, 16 1x to 4x driver inputs 5 gnd ground 4 v cc supply voltage input enables outputs a #en #y #z lhlh hhhl open h l h xlzz xxzz symbol parameter value unit v cc supply voltage (note 1) -0.5 to 4 v v r voltage range enable inputs -0.5 to 6 v a, y or z -0.5 to 4 v esd esd protection voltage (hbm) y, z, to gnd 7 kv all pins 2 kv t stg storage temperature range -65 to +150 c
stlvds105 3/8 recommended operating conditions electrical characteristics (t a = -40 to 85c, and v cc = 3.3v 10% over recommended operating conditions unless otherwise noted. all typical values are at t a =25c) symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v v ih high level input voltage 2.0 v v il low level input voltage 0.8 v |v id | magnitude of differential input voltage 0.1 3.6 v v ic common mode input voltage |v id |/2 24-|v id |/2 v v cc -0.8 t a operating temperature range -40 85 c symbol parameter test conditions min. typ. max. unit |v od | differential output voltage magnitude r l = 100 w v id = 100mv 247 350 454 mv d| v od | change in differential output voltage magnitude between logic state -25 25 mv d v oc(ss) change in steady-state common mode output voltage between logic state -25 25 mv v oc(ss) steady-state common mode output voltage 1.125 1.2 1.375 v v oc(pp) peak to paek common mode output voltage 25 150 mv i cc supply current enabled, r l =100 w 18 28 ma disabled 0.3 1 ma i ih high level input current v ih =2v 7 20 m a i il low level input current v il = 0.8v 3 10 m a i oc short circuit output current v o(y) or v o(z) =0v 10 ma v od =0 10 ma i oz high impedance output current v o = 0 or 2.4v 1 m a i o(off) power off output current v cc = 1.5v v o = 2.4v 0.3 1 m a c in input capacitance (a or b inputs) v i = 0.4 sin (4e 6 p t )+0.5v 5pf c o output capacitance (y or z outputs) v i = 0.4 sin (4e 6 p t )+0.5v, disabled 9.4 pf
stlvds105 4/8 switching characteristics (t a = -40 to 85c, and v cc = 3.3v unless otherwise noted. all typical values are at t a = 25c) note 1: t sk(o) isthetimedifferencebetweenthet plh or t phl of all drivers of a single device with all their inputs connected together. note 2: t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuit. symbol parameter test conditions min. typ. max. unit t plh propagation delay time, low to high output r l = 100 w c l = 10pf 1.7 2.2 3 ns t phl propagation delay time, high to low output 1.7 2.2 3 ns t r differential output signal rise time 0.3 0.5 0.8 ns t f differential output signal fall time 0.3 0.5 0.8 ns t sk(p) pulse skew (|t thl -t tlh |) 50 200 ps t sk(o) channel-to-channel output skew (note1) 30 100 ps t sk(pp) part to part skew (note2) 1.5 ns t pzh propagation delay time, high impedance to high level output 510ns t pzl propagation delay time, high impedance to low level output 510ns t phz propagation delay time, high level to high impedance output 410ns t plz propagation delay time, low level to high impedance output 510ns
stlvds105 5/8 typical performance characteristics (unless otherwise specified t j = 25c) figure 1 : output current vs output high voltage figure 2 : output current vs output low voltage figure 3 : high to low propagation delay time figure 4 : low to high propagation delay time
stlvds105 6/8 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.004 0.008 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45? (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 ? (max.) so-16 mechanical data po13h
stlvds105 7/8 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0? 8?0? 8? l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
stlvds105 8/8 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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